PipeRench: A Reconfigurable Architecture and Compiler

H ighly specialized embedded computer systems abound, and workloads for computing devices are rapidly changing. General– purpose processors are struggling to efficiently meet these applications’ disparate needs, and custom hardware is rarely feasible. The time is ripe for reconfigurable computing, which combines the flexibility of general-purpose processors with the efficiency of custom hardware. PipeRench, a new architecture for reconfigurable computing, and its associated compiler do just that. Combined with a traditional digital signal processor, microcontroller, or general-purpose processor, PipeRench can support a system’s various computing needs without requiring custom hardware. PipeRench is a reconfigurable fabric—an interconnected parallel-processing network of logic and storage processing elements. By virtualizing the hardware, PipeRench overcomes the disadvantages of using fieldprogrammable gate arrays as reconfigurable computing fabrics. Unlike FPGAs, PipeRench is designed to efficiently handle computations. Using a technique called pipeline reconfiguration, PipeRench improves compilation time, reconfiguration time, and forward compatibility. PipeRench’s architectural parameters (including logic block granularity) optimize the performance of a suite of kernels, balancing the compiler’s needs against the constraints of deep-submicron process technology. PipeRench is particularly suitable for stream-based media applications or any applications that rely on simple, regular computations on large sets of small data elements. Conventional processors lag in efficiency because of forced serialization of intrinsically parallel operations; wasted space (small data elements do not use the processor’s wide data path); and excessive instruction bandwidth for regular, dataflow-dominated computations on large data sets. A system using a reconfigurable fabric such as PipeRench can